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Merge pull request #1046 from efiop/master

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test: cover pipeline show --ascii
This commit is contained in:
Ruslan Kuprieiev
2018-08-23 08:07:47 +03:00
committed by GitHub
parent a7f14c2d3c 26e007f407
commit f682e556ec
2 changed files with 16 additions and 0 deletions
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dvc/command/pipeline.py
+4
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@@ -63,6 +63,10 @@ class CmdPipelineShow(CmdBase):
nodes.add(to_stage.relpath)
edges.append((from_stage.relpath, to_stage.relpath))
nodes = list(nodes)
if len(nodes) == 0:
return
d = Dagascii(nodes, edges)
d.draw()
tests/test_pipeline.py
+12
View File
@@ -16,6 +16,18 @@ class TestPipelineShow(TestRepro):
ret = main(['pipeline', 'show', self.file1_stage, '--outs'])
self.assertEqual(ret, 0)
def test_ascii(self):
ret = main(['pipeline', 'show', '--ascii', self.file1_stage])
self.assertEqual(ret, 0)
def test_ascii_commands(self):
ret = main(['pipeline', 'show', '--ascii', self.file1_stage, '--commands'])
self.assertEqual(ret, 0)
def test_ascii_outs(self):
ret = main(['pipeline', 'show', '--ascii', self.file1_stage, '--outs'])
self.assertEqual(ret, 0)
def test_not_dvc_file(self):
ret = main(['pipeline', 'show', self.file1])
self.assertNotEqual(ret, 0)