From 26e007f407002e6133e0779d5af19a5c951ace9a Mon Sep 17 00:00:00 2001 From: Ruslan Kuprieiev Date: Thu, 23 Aug 2018 07:57:09 +0300 Subject: [PATCH] test: cover pipeline show --ascii Signed-off-by: Ruslan Kuprieiev --- dvc/command/pipeline.py | 4 ++++ tests/test_pipeline.py | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/dvc/command/pipeline.py b/dvc/command/pipeline.py index 3ccb50487..b73bb8de2 100644 --- a/dvc/command/pipeline.py +++ b/dvc/command/pipeline.py @@ -63,6 +63,10 @@ class CmdPipelineShow(CmdBase): nodes.add(to_stage.relpath) edges.append((from_stage.relpath, to_stage.relpath)) + nodes = list(nodes) + if len(nodes) == 0: + return + d = Dagascii(nodes, edges) d.draw() diff --git a/tests/test_pipeline.py b/tests/test_pipeline.py index 287f17468..265ed47e9 100644 --- a/tests/test_pipeline.py +++ b/tests/test_pipeline.py @@ -16,6 +16,18 @@ class TestPipelineShow(TestRepro): ret = main(['pipeline', 'show', self.file1_stage, '--outs']) self.assertEqual(ret, 0) + def test_ascii(self): + ret = main(['pipeline', 'show', '--ascii', self.file1_stage]) + self.assertEqual(ret, 0) + + def test_ascii_commands(self): + ret = main(['pipeline', 'show', '--ascii', self.file1_stage, '--commands']) + self.assertEqual(ret, 0) + + def test_ascii_outs(self): + ret = main(['pipeline', 'show', '--ascii', self.file1_stage, '--outs']) + self.assertEqual(ret, 0) + def test_not_dvc_file(self): ret = main(['pipeline', 'show', self.file1]) self.assertNotEqual(ret, 0)