dvc: properly resolve cwd for dvc add

Fixes #943

Signed-off-by: Ruslan Kuprieiev <[email protected]>

dvc/project.py

@@ -131,7 +131,8 @@ class Project(object):
 
     def add(self, fname):
         stage = Stage.loads(project=self,
-                            outs=[fname])
+                            outs=[fname],
+                            add=True)
 
         stage.save()
         stage.dump()

dvc/stage.py

@@ -185,7 +185,7 @@ class Stage(object):
         return stage
 
     @classmethod
-    def _stage_fname_cwd(cls, fname, cwd, outs):
+    def _stage_fname_cwd(cls, fname, cwd, outs, add):
         if fname and cwd:
             return (fname, cwd)
 
@@ -199,7 +199,7 @@ class Stage(object):
             path = posixpath
 
         fname = fname if fname else path.basename(out.path) + cls.STAGE_FILE_SUFFIX
-        cwd = cwd if cwd else path.dirname(out.path)
+        cwd = path.dirname(out.path) if not cwd or add else cwd
 
         return (fname, cwd)
 
@@ -212,7 +212,8 @@ class Stage(object):
               metrics_no_cache=[],
               fname=None,
               cwd=os.curdir,
-              locked=False):
+              locked=False,
+              add=False):
         stage = Stage(project=project,
                       cwd=cwd,
                       cmd=cmd,
@@ -223,7 +224,7 @@ class Stage(object):
         stage.outs += output.loads_from(stage, metrics_no_cache, use_cache=False, metric=True)
         stage.deps = dependency.loads_from(stage, deps)
 
-        fname, cwd = Stage._stage_fname_cwd(fname, cwd, stage.outs)
+        fname, cwd = Stage._stage_fname_cwd(fname, cwd, stage.outs, add=add)
 
         cwd = os.path.abspath(cwd)
         path = os.path.join(cwd, fname)

tests/test_add.py

@@ -88,6 +88,15 @@ class TestAddModifiedDir(TestDvc):
         self.dvc.add(self.DATA_DIR)
 
 
+class TestAddFileInDir(TestDvc):
+    def test(self):
+        stage = self.dvc.add(self.DATA_SUB)
+        self.assertNotEqual(stage, None)
+        self.assertEqual(len(stage.deps), 0)
+        self.assertEqual(len(stage.outs), 1)
+        self.assertEqual(stage.relpath, self.DATA_SUB + '.dvc')
+
+
 class TestCmdAdd(TestDvc):
     def test(self):
         ret = main(['add',