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https://github.com/Stone-Red-Code/StoneRed.LogicSimulator.git
synced 2026-09-04 00:56:23 +02:00
Add new cycle and event based simulator for better performance and associated unit tests
This commit is contained in:
Stone_Red
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using Microsoft.VisualStudio.TestTools.UnitTesting;
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using StoneRed.LogicSimulator.Simulation;
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namespace StoneRed.LogicSimulator.Tests;
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[TestClass]
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public class CycleAdvancedTests : AdvancedCircuitTestsBase
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{
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protected override ICircuitSimulator CreateSimulator()
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{
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return new CycleCircuitSimulator();
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}
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}
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[TestClass]
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public class EventAdvancedTests : AdvancedCircuitTestsBase
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{
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protected override ICircuitSimulator CreateSimulator()
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{
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return new EventCircuitSimulator();
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}
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}
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public abstract class AdvancedCircuitTestsBase
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{
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protected abstract ICircuitSimulator CreateSimulator();
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[TestMethod]
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public void TestSRLatch()
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{
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// SR Latch using NOR gates
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// Q = NOR(R, Q')
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// Q' = NOR(S, Q)
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ICircuitSimulator sim = CreateSimulator();
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int s = sim.AddGate(GateKind.Source);
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int r = sim.AddGate(GateKind.Source);
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int orQ = sim.AddGate(GateKind.Or2);
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int norQ = sim.AddGate(GateKind.Not); // Q
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int orQNot = sim.AddGate(GateKind.Or2);
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int norQNot = sim.AddGate(GateKind.Not); // Q'
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// Q = NOR(R, Q')
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sim.ConnectGates(r, orQ, 0);
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sim.ConnectGates(norQNot, orQ, 1);
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sim.ConnectGates(orQ, norQ, 0);
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// Q' = NOR(S, Q)
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sim.ConnectGates(s, orQNot, 0);
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sim.ConnectGates(norQ, orQNot, 1);
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sim.ConnectGates(orQNot, norQNot, 0);
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int qSink = sim.AddGate(GateKind.Sink);
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int qNotSink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(norQ, qSink, 0);
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sim.ConnectGates(norQNot, qNotSink, 0);
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// Reset state (R=1, S=0) -> Q=0, Q'=1
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sim.SetSource(r, true);
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sim.SetSource(s, false);
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_ = sim.RunUntilStable(10000);
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Assert.IsFalse(sim.GetOutput(qSink), "Q should be 0 after Reset (R=1)");
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Assert.IsTrue(sim.GetOutput(qNotSink), "Q' should be 1 after Reset (R=1)");
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// Hold (R=0, S=0) -> Q=0
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sim.SetSource(r, false);
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_ = sim.RunUntilStable(10000);
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Assert.IsFalse(sim.GetOutput(qSink), "Q should stay 0");
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// Set state (R=0, S=1) -> Q=1, Q'=0
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sim.SetSource(s, true);
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_ = sim.RunUntilStable(10000);
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Assert.IsTrue(sim.GetOutput(qSink), "Q should be 1 after Set (S=1)");
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Assert.IsFalse(sim.GetOutput(qNotSink), "Q' should be 0 after Set (S=1)");
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// Hold (R=0, S=0) -> Q=1
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sim.SetSource(s, false);
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_ = sim.RunUntilStable(10000);
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Assert.IsTrue(sim.GetOutput(qSink), "Q should stay 1");
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}
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[TestMethod]
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public void TestFullAdder()
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{
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ICircuitSimulator sim = CreateSimulator();
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int a = sim.AddGate(GateKind.Source);
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int b = sim.AddGate(GateKind.Source);
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int cin = sim.AddGate(GateKind.Source);
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int[] xorTable = { 0, 1, 1, 0 };
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int xor1 = sim.AddLutGate(2, xorTable);
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int xor2 = sim.AddLutGate(2, xorTable);
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int and1 = sim.AddGate(GateKind.And2);
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int and2 = sim.AddGate(GateKind.And2);
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int or1 = sim.AddGate(GateKind.Or2);
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sim.ConnectGates(a, xor1, 0);
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sim.ConnectGates(b, xor1, 1);
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sim.ConnectGates(xor1, xor2, 0);
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sim.ConnectGates(cin, xor2, 1);
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sim.ConnectGates(a, and1, 0);
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sim.ConnectGates(b, and1, 1);
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sim.ConnectGates(xor1, and2, 0);
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sim.ConnectGates(cin, and2, 1);
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sim.ConnectGates(and1, or1, 0);
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sim.ConnectGates(and2, or1, 1);
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int sumSink = sim.AddGate(GateKind.Sink);
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int coutSink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(xor2, sumSink, 0);
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sim.ConnectGates(or1, coutSink, 0);
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void Check(bool iA, bool iB, bool iC, bool expectedSum, bool expectedCout)
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{
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sim.SetSource(a, iA);
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sim.SetSource(b, iB);
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sim.SetSource(cin, iC);
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_ = sim.RunUntilStable(10000);
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Assert.AreEqual(expectedSum, sim.GetOutput(sumSink), $"Sum failed for {iA},{iB},{iC}");
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Assert.AreEqual(expectedCout, sim.GetOutput(coutSink), $"Cout failed for {iA},{iB},{iC}");
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}
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Check(false, false, false, false, false);
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Check(true, false, false, true, false);
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Check(false, true, false, true, false);
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Check(true, true, false, false, true);
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Check(false, false, true, true, false);
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Check(true, false, true, false, true);
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Check(false, true, true, false, true);
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Check(true, true, true, true, true);
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}
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[TestMethod]
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public void TestDLatch()
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{
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ICircuitSimulator sim = CreateSimulator();
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int dSource = sim.AddGate(GateKind.Source);
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int enSource = sim.AddGate(GateKind.Source);
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int notD = sim.AddGate(GateKind.Not);
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sim.ConnectGates(dSource, notD, 0);
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int sAnd = sim.AddGate(GateKind.And2);
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sim.ConnectGates(dSource, sAnd, 0);
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sim.ConnectGates(enSource, sAnd, 1);
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int rAnd = sim.AddGate(GateKind.And2);
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sim.ConnectGates(notD, rAnd, 0);
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sim.ConnectGates(enSource, rAnd, 1);
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int orQ = sim.AddGate(GateKind.Or2);
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int norQ = sim.AddGate(GateKind.Not);
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int orQNot = sim.AddGate(GateKind.Or2);
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int norQNot = sim.AddGate(GateKind.Not);
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sim.ConnectGates(rAnd, orQ, 0);
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sim.ConnectGates(norQNot, orQ, 1);
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sim.ConnectGates(orQ, norQ, 0);
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sim.ConnectGates(sAnd, orQNot, 0);
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sim.ConnectGates(norQ, orQNot, 1);
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sim.ConnectGates(orQNot, norQNot, 0);
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int qSink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(norQ, qSink, 0);
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// 1. Transparent mode (EN=1) -> Q follows D
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sim.SetSource(enSource, true);
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sim.SetSource(dSource, true);
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_ = sim.RunUntilStable(10000);
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Assert.IsTrue(sim.GetOutput(qSink), "Q should be 1 when D=1, EN=1");
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sim.SetSource(dSource, false);
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_ = sim.RunUntilStable(10000);
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Assert.IsFalse(sim.GetOutput(qSink), "Q should be 0 when D=0, EN=1");
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// 2. Latch mode (EN=0) -> Q stays same
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sim.SetSource(dSource, true);
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sim.SetSource(enSource, true);
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_ = sim.RunUntilStable(10000);
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Assert.IsTrue(sim.GetOutput(qSink));
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sim.SetSource(enSource, false); // LATCH
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_ = sim.RunUntilStable(10000);
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sim.SetSource(dSource, false); // Change D while latched
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_ = sim.RunUntilStable(10000);
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Assert.IsTrue(sim.GetOutput(qSink), "Q should stay 1 even if D changes while EN=0");
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}
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}
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@@ -0,0 +1,157 @@
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using Microsoft.VisualStudio.TestTools.UnitTesting;
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using StoneRed.LogicSimulator.Simulation;
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namespace StoneRed.LogicSimulator.Tests;
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[TestClass]
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public class CycleSimulatorTests : SimulatorTestsBase
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{
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protected override ICircuitSimulator CreateSimulator()
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{
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return new CycleCircuitSimulator();
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}
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}
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[TestClass]
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public class EventSimulatorTests : SimulatorTestsBase
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{
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protected override ICircuitSimulator CreateSimulator()
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{
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return new EventCircuitSimulator();
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}
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}
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public abstract class SimulatorTestsBase
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{
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protected abstract ICircuitSimulator CreateSimulator();
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[TestMethod]
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public void TestAndGate()
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{
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ICircuitSimulator sim = CreateSimulator();
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int s1 = sim.AddGate(GateKind.Source);
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int s2 = sim.AddGate(GateKind.Source);
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int and = sim.AddGate(GateKind.And2);
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int sink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(s1, and, 0);
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sim.ConnectGates(s2, and, 1);
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sim.ConnectGates(and, sink, 0);
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void Check(bool i1, bool i2, bool expected)
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{
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sim.SetSource(s1, i1);
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sim.SetSource(s2, i2);
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_ = sim.RunUntilStable();
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Assert.AreEqual(expected, sim.GetOutput(sink), $"AND2 failed for {i1} & {i2}");
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}
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sim.Reset();
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Check(false, false, false);
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Check(false, true, false);
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Check(true, false, false);
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Check(true, true, true);
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}
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[TestMethod]
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public void TestOrGate()
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{
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ICircuitSimulator sim = CreateSimulator();
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int s1 = sim.AddGate(GateKind.Source);
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int s2 = sim.AddGate(GateKind.Source);
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int or = sim.AddGate(GateKind.Or2);
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int sink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(s1, or, 0);
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sim.ConnectGates(s2, or, 1);
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sim.ConnectGates(or, sink, 0);
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void Check(bool i1, bool i2, bool expected)
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{
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sim.SetSource(s1, i1);
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sim.SetSource(s2, i2);
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_ = sim.RunUntilStable();
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Assert.AreEqual(expected, sim.GetOutput(sink), $"OR2 failed for {i1} | {i2}");
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}
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sim.Reset();
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Check(false, false, false);
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Check(false, true, true);
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Check(true, false, true);
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Check(true, true, true);
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}
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[TestMethod]
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public void TestNotGate()
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{
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ICircuitSimulator sim = CreateSimulator();
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int s1 = sim.AddGate(GateKind.Source);
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int not = sim.AddGate(GateKind.Not);
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int sink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(s1, not, 0);
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sim.ConnectGates(not, sink, 0);
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sim.Reset();
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sim.SetSource(s1, false);
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_ = sim.RunUntilStable();
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Assert.IsTrue(sim.GetOutput(sink), "NOT(0) should be 1");
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sim.SetSource(s1, true);
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_ = sim.RunUntilStable();
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Assert.IsFalse(sim.GetOutput(sink), "NOT(1) should be 0");
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}
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[TestMethod]
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public void TestLutGate()
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{
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ICircuitSimulator sim = CreateSimulator();
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int s1 = sim.AddGate(GateKind.Source);
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int s2 = sim.AddGate(GateKind.Source);
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int s3 = sim.AddGate(GateKind.Source);
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// Majority function (2 or more high)
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int[] table = { 0, 0, 0, 1, 0, 1, 1, 1 };
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int lut = sim.AddLutGate(3, table);
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int sink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(s1, lut, 0);
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sim.ConnectGates(s2, lut, 1);
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sim.ConnectGates(s3, lut, 2);
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sim.ConnectGates(lut, sink, 0);
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sim.Reset();
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_ = sim.RunUntilStable();
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sim.SetSource(s1, true); sim.SetSource(s2, true); sim.SetSource(s3, false);
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_ = sim.RunUntilStable();
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Assert.IsTrue(sim.GetOutput(sink), "Majority(1,1,0) should be 1");
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sim.SetSource(s1, false); sim.SetSource(s2, true); sim.SetSource(s3, false);
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_ = sim.RunUntilStable();
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Assert.IsFalse(sim.GetOutput(sink), "Majority(0,1,0) should be 0");
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}
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[TestMethod]
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public void TestMacroCorrectness()
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{
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ICircuitSimulator sim = CreateSimulator();
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CircuitDefinition def = new CircuitDefinition();
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int inPin = def.AddInputPin();
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int not = def.AddGate(GateKind.Not);
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int outPin = def.AddOutputPin();
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def.Connect(inPin, not, 0);
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def.Connect(not, outPin, 0);
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sim.RegisterMacroGate("NOT", def);
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MacroInstance inst = sim.AddMacroGate("NOT");
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int src = sim.AddGate(GateKind.Source);
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int sink = sim.AddGate(GateKind.Sink);
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sim.ConnectGates(src, inst.Inputs[0], 0);
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sim.ConnectGates(inst.Outputs[0], sink, 0);
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sim.Reset();
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sim.SetSource(src, true);
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_ = sim.RunUntilStable();
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Assert.IsFalse(sim.GetOutput(sink), "Macro NOT(1) should be 0");
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}
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}
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@@ -0,0 +1,18 @@
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<Project Sdk="Microsoft.NET.Sdk">
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<PropertyGroup>
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<TargetFramework>net8.0</TargetFramework>
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<ImplicitUsings>enable</ImplicitUsings>
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<Nullable>enable</Nullable>
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<IsPackable>false</IsPackable>
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</PropertyGroup>
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<ItemGroup>
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<PackageReference Include="Microsoft.NET.Test.Sdk" Version="17.8.0" />
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<PackageReference Include="MSTest.TestAdapter" Version="3.1.1" />
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<PackageReference Include="MSTest.TestFramework" Version="3.1.1" />
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</ItemGroup>
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<ItemGroup>
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<ProjectReference Include="..\StoneRed.LogicSimulator.Simulation\StoneRed.LogicSimulator.Simulation.csproj" />
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</ItemGroup>
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</Project>
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